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| FDS6612A June 2003 FDS6612A Single N-Channel, Logic-Level, PowerTrench(R) MOSFET General Description This N-Channel Logic Level MOSFET is produced using Fairchild Semiconductor's advanced PowerTrench process that has been especially tailored to minimize the on-state resistance and yet maintain superior switching performance. These devices are well suited for low voltage and battery powered applications where low in-line power loss and fast switching are required. Features * 8.4 A, 30 V. RDS(ON) = 22 m @ VGS = 10 V RDS(ON) = 30 m @ VGS = 4.5 V * Fast switching speed * Low gate charge * High performance trench technology for extremely low RDS(ON) * High power and current handling capability D D D D SO-8 DD D D 5 6 7 4 3 2 1 Pin 1 SO-8 G SG S S SS S TA=25oC unless otherwise noted 8 Absolute Maximum Ratings Symbol VDSS VGSS ID PD TJ, TSTG Drain-Source Voltage Gate-Source Voltage Drain Current - Continuous - Pulsed Parameter Ratings 30 20 (Note 1a) Units V V A W C 8.4 40 2.5 1.0 -55 to +150 Power Dissipation for Single Operation (Note 1a) (Note 1b) Operating and Storage Junction Temperature Range Thermal Characteristics RJA RJA RJC Thermal Resistance, Junction-to-Ambient Thermal Resistance, Junction-to-Ambient Thermal Resistance, Junction-to-Case (Note 1a) (Note 1b) (Note 1) 50 125 25 C/W Package Marking and Ordering Information Device Marking FDS6612A Device FDS6612A Reel Size 13'' Tape width 12mm Quantity 2500 units (c)2003 Fairchild Semiconductor Corporation FDS6612A Rev D (W) FDS6612A Electrical Characteristics Symbol BVDSS BVDSS TJ IDSS IGSS TA = 25C unless otherwise noted Parameter Drain-Source Breakdown Voltage Breakdown Voltage Temperature Coefficient Zero Gate Voltage Drain Current Gate-Body Leakage (Note 2) Test Conditions VGS = 0 V, ID = 250 A Min Typ 30 26 Max Units V mV/C Off Characteristics ID = 250 A, Referenced to 25C VDS = 24 V, VGS = 20 V, VGS = 0 V VDS = 0 V 1 10 100 A A nA VDS = 24 V, VGS = 0 V, TJ=55C On Characteristics VGS(th) VGS(th) TJ RDS(on) Gate Threshold Voltage Gate Threshold Voltage Temperature Coefficient Static Drain-Source On-Resistance On-State Drain Current Forward Transconductance VDS = VGS, ID = 250 A ID = 250 A, Referenced to 25C VGS = 10 V, ID = 8.4 A VGS = 4.5 V, ID = 7.2 A VGS= 10 V, ID = 8.4 A, TJ=125C VGS = 10 V, VDS = 15 V, VDS = 5 V ID = 8.4 A 1 1.9 -4.4 19 24 25 3 V mV/C 22 30 37 m ID(on) gFS 20 30 A S Dynamic Characteristics Ciss Coss Crss RG Input Capacitance Output Capacitance Reverse Transfer Capacitance Gate Resistance (Note 2) VDS = 15 V, f = 1.0 MHz V GS = 0 V, 560 140 55 2.5 pF pF pF 14 10 35 6 7.6 ns ns ns ns nC nC nC VGS = 15 mV, f = 1.0 MHz Switching Characteristics td(on) tr td(off) tf Qg Qgs Qgd Turn-On Delay Time Turn-On Rise Time Turn-Off Delay Time Turn-Off Fall Time Total Gate Charge Gate-Source Charge Gate-Drain Charge VDD = 15 V, VGS = 10 V, ID = 1 A, RGEN = 6 7 5 22 3 VDS = 15 V, VGS = 5 V ID = 8.4 A, 5.4 1.7 1.9 Drain-Source Diode Characteristics and Maximum Ratings IS VSD trr Qrr Maximum Continuous Drain-Source Diode Forward Current Drain-Source Diode Forward VGS = 0 V, IS = 2.1 A (Note 2) Voltage Diode Reverse Recovery Time IF = 8.4 A, diF/dt = 100 A/s Diode Reverse Recovery Charge 2.1 0.77 19 9 1.2 A V nS nC Notes: 1. RJA is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. RJC is guaranteed by design while RCA is determined by the user's board design. a) 50C/W when mounted on a 1in2 pad of 2 oz copper b) 125C/W when mounted on a minimum pad. Scale 1 : 1 on letter size paper 2 Test: Pulse Width < 300s, Duty Cycle < 2.0% FDS6612A Rev D (W) FDS6612A Typical Characteristics 40 VGS = 10V 4.5V 2 VGS = 3.5V RDS(ON), NORMALIZED DRAIN-SOURCE ON-RESISTANCE 4.0V 1.8 ID, DRAIN CURRENT (A) 30 6.0V 1.6 4.0V 1.4 4.5V 1.2 5.0V 6.0V 10V 1 20 3.5V 10 3.0V 0 0 0.5 1 1.5 2 2.5 VDS, DRAIN TO SOURCE VOLTAGE (V) 3 0.8 0 10 20 ID, DRAIN CURRENT (A) 30 40 Figure 1. On-Region Characteristics. Figure 2. On-Resistance Variation with Drain Current and Gate Voltage. 0.1 RDS(ON), ON-RESISTANCE (OHM) 1.6 RDS(ON), NORMALIZED DRAIN-SOURCE ON-RESISTANCE ID = 8.4A VGS = 10V 1.4 ID = 4.2A 0.08 1.2 0.06 TA = 125oC 0.04 TA = 25oC 0.02 1 0.8 0.6 -50 -25 0 25 50 75 100 TJ, JUNCTION TEMPERATURE (oC) 125 150 0 2 4 6 8 VGS, GATE TO SOURCE VOLTAGE (V) 10 Figure 3. On-Resistance Variation with Temperature. 40 Figure 4. On-Resistance Variation with Gate-to-Source Voltage. 100 IS, REVERSE DRAIN CURRENT (A) VDS = 5V ID, DRAIN CURRENT (A) 30 VGS = 0V 10 1 TA = 125 C o 20 0.1 TA = 125oC -55 C 10 o 25oC -55 C o 0.01 0.001 25oC 0 1.5 2 2.5 3 3.5 VGS, GATE TO SOURCE VOLTAGE (V) 4 4.5 0.0001 0 0.2 0.4 0.6 0.8 1 VSD, BODY DIODE FORWARD VOLTAGE (V) 1.2 Figure 5. Transfer Characteristics. Figure 6. Body Diode Forward Voltage Variation with Source Current and Temperature. FDS6612A Rev D (W) FDS6612A Typical Characteristics 10 VGS, GATE-SOURCE VOLTAGE (V) ID = 8.4A 8 VDS = 10V 20V 6 15V 4 CAPACITANCE (pF) 800 f = 1 MHz VGS = 0 V 600 Ciss 400 Coss 200 2 Crss 0 0 2 4 6 8 Qg, GATE CHARGE (nC) 10 12 0 0 5 10 15 20 VDS, DRAIN TO SOURCE VOLTAGE (V) 25 30 Figure 7. Gate Charge Characteristics. 100 100s RDS(ON) LIMIT P(pk), PEAK TRANSIENT POWER (W) 50 Figure 8. Capacitance Characteristics. ID, DRAIN CURRENT (A) 10 1ms 10ms 100ms 1s 10s DC 40 SINGLE PULSE o RJA = 125 C/W TA = 25oC 30 1 20 0.1 VGS = 10V SINGLE PULSE RJA = 125oC/W TA = 25 C o 10 0.01 0.01 0.1 1 10 VDS, DRAIN-SOURCE VOLTAGE (V) 100 0 0.001 0.01 0.1 1 t1, TIME (sec) 10 100 Figure 9. Maximum Safe Operating Area. Figure 10. Single Pulse Maximum Power Dissipation. r(t), NORMALIZED EFFECTIVE TRANSIENT THERMAL RESISTANCE 1 D = 0.5 0.2 RJA(t) = r(t) * RJA RJA = 125 C/W P(pk) t1 t2 SINGLE PULSE o 0.1 0.1 0.05 0.02 0.01 0.01 TJ - TA = P * RJA(t) Duty Cycle, D = t1 / t2 0.001 0.0001 0.001 0.01 0.1 t1, TIME (sec) 1 10 100 1000 Figure 11. Transient Thermal Response Curve. Thermal characterization performed using the conditions described in Note 1c. Transient thermal response will change depending on the circuit board design. FDS6612A Rev D (W) FDS6612A PSPICE Electrical Model N-Channel .SUBCKT FDS6612A 2 1 3 *NOM TEMP=25 DEG C *REV A - JULY 2003 CA 12 8 1E-9 CB 15 14 4.0E-10 CIN 6 8 5.1E-10 DBODY 7 5 DBODYMOD DBREAK 5 11 DBREAKMOD DPLCAP 10 5 DPLCAPMOD EBREAK 11 7 17 18 34.2 EDS 14 8 5 8 1 EGS 13 8 6 8 1 ESG 6 10 6 8 1 EVTHRES 6 21 19 8 1 EVTEMP 20 6 18 22 1 IT 8 17 1 LGATE 1 9 3.84E-9 LDRAIN 2 5 1.00E-9 LSOURCE 3 7 4E-9 RLGATE 1 9 38.4 RLDRAIN 2 5 10 RLSOURCE 3 7 40 MMED 16 6 8 8 MMEDMOD MSTRO 16 6 8 8 MSTROMOD MWEAK 16 21 8 8 MWEAKMOD RBREAK 17 18 RBREAKMOD 1 RDRAIN 50 16 RDRAINMOD 8E-3 RGATE 9 20 4.2 RSLC1 5 51 RSLCMOD 1E-6 RSLC2 5 50 1E3 RSOURCE 8 7 RSOURCEMOD 7.5E-3 RVTHRES 22 8 RVTHRESMOD 1 RVTEMP 18 19 RVTEMPMOD 1 S1A 6 12 13 8 S1AMOD S1B 13 12 13 8 S1BMOD S2A 6 15 14 13 S2AMOD S2B 13 15 14 13 S2BMOD VBAT 22 19 DC 1 ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1E-6*105),3))} .MODEL DBODYMOD D (IS=7E-15 RS=6.1E-3 N=0.84 TRS1=1.7E-3 TRS2=1.0E-6 + CJO=3.2E-10 TT=10E-9 M=0.5 IKF=0.3 XTI=3.0) .MODEL DBREAKMOD D (RS=1E-1 TRS1=1.12E-3 TRS2=1.25E-6) .MODEL DPLCAPMOD D (CJO=14E-11 IS=1E-30 N=10 M=0.34) .MODEL MWEAKMOD NMOS (VTO=1.82 KP=0.05 IS=1E-30 N=10 TOX=1 L=1U W=1U RG=42 RS=.1) .MODEL MMEDMOD NMOS (VTO=2.1 KP=6 IS=1E-30 N=10 TOX=1 L=1U W=1U RG=4.2) .MODEL MSTROMOD NMOS (VTO=2.55 KP=50 IS=1E-30 N=10 TOX=1 L=1U W=1U) .MODEL RBREAKMOD RES (TC1=0.83E-3 TC2=1E-7) .MODEL RDRAINMOD RES (TC1=6E-3 TC2=5E-6) .MODEL RSLCMOD RES (TC1=2.5E-3 TC2=4.5E-6) .MODEL RSOURCEMOD RES (TC1=1.0E-3 TC2=1E-6) .MODEL RVTHRESMOD RES (TC1=-2.013E-3 TC2=-7E-6) .MODEL RVTEMPMOD RES (TC1=-1.5E-3 TC2=1E-6) .MODEL S1AMOD VSWITCH (RON=1E-5 ROFF=0.1 VON=-4 VOFF=-3) .MODEL S1BMOD VSWITCH (RON=1E-5 ROFF=0.1 VON=-3 VOFF=-4) .MODEL S2AMOD VSWITCH (RON=1E-5 ROFF=0.1 VON=-1.3 VOFF=-0.5) .MODEL S2BMOD VSWITCH (RON=1E-5 ROFF=0.1 VON=-0.5 VOFF=-1.3) .ENDS Note: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley. FDS6612A Rev D (W) LDRAIN DPLCAP 10 RSLC1 51 RSLC2 5 51 ESG + LGATE GATE 1 RLGATE CIN EVTEMP RGATE + 18 9 20 22 6 8 EVTHRES + 19 8 6 MSTRO LSOURCE 8 RSOURCE RLSOURCE S1A 12 13 8 S1B CA 13 + EGS 6 8 EDS S2A 14 13 S2B CB + 5 8 8 22 RVTHRES 14 IT 15 17 RBREAK 18 RVTEMP 19 VBAT + 7 SOURC E 3 50 RDRAIN 21 16 MWEAK MMED EBREAK + ESLC RLDRAIN DBREAK 5 DRAIN 2 11 + 17 18 D BODY FDS6612A SPICE Thermal Model .SUBCKT FDS6612A_THERM TH TL *THERMAL MODEL SUBCIRCUIT *REV A - JULY 2003 *MIN PAD RJA RTHERM1 th JUNCTION CTHERM1 8 CTHERM1 CTHERM2 CTHERM3 CTHERM4 CTHERM5 CTHERM6 CTHERM7 CTHERM8 RTHERM1 RTHERM2 RTHERM3 RTHERM4 RTHERM5 RTHERM6 RTHERM7 RTHERM8 .ENDS TH 8 7 6 5 4 3 2 TH 8 7 6 5 4 3 2 8 7 6 5 4 3 2 TL 8 7 6 5 4 3 2 TL 0.005 0.05 0.10 0.35 0.45 0.50 0.55 3.00 5.000 6.250 7.500 8.750 10.625 11.875 31.250 43.750 RTHERM2 7 RTHERM3 6 RTHERM4 5 CTHERM2 CTHERM3 CTHERM4 RTHERM5 4 CTHERM5 RTHERM6 3 CTHERM6 RTHERM7 2 RTHERM8 CTHERM7 CTHERM8 tl AMBIENT FDS6612A Rev D (W) TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. ACExTM FACT Quiet SeriesTM ActiveArrayTM FAST BottomlessTM FASTrTM CoolFETTM FRFETTM CROSSVOLTTM GlobalOptoisolatorTM DOMETM GTOTM EcoSPARKTM HiSeCTM E2CMOSTM I2CTM TM EnSigna ImpliedDisconnectTM FACTTM ISOPLANARTM Across the board. Around the world.TM The Power FranchiseTM Programmable Active DroopTM DISCLAIMER LittleFETTM MICROCOUPLERTM MicroFETTM MicroPakTM MICROWIRETM MSXTM MSXProTM OCXTM OCXProTM OPTOLOGIC OPTOPLANARTM PACMANTM POPTM Power247TM PowerTrench QFET QSTM QT OptoelectronicsTM Quiet SeriesTM RapidConfigureTM RapidConnectTM SILENT SWITCHER SMART STARTTM SPMTM StealthTM SuperSOTTM-3 SuperSOTTM-6 SuperSOTTM-8 SyncFETTM TinyLogic TINYOPTOTM TruTranslationTM UHCTM UltraFET VCXTM FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component is any component of a life 1. Life support devices or systems are devices or support device or system whose failure to perform can systems which, (a) are intended for surgical implant into be reasonably expected to cause the failure of the life the body, or (b) support or sustain life, or (c) whose support device or system, or to affect its safety or failure to perform when properly used in accordance with instructions for use provided in the labeling, can be effectiveness. reasonably expected to result in significant injury to the user. PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Advance Information Product Status Formative or In Design Definition This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. Preliminary First Production No Identification Needed Full Production Obsolete Not In Production This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only. Rev. I5 |
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